#ifndef __FULLHAN_CHIP_H__
#define __FULLHAN_CHIP_H__

#include <linux/init.h>

#define DMAC0_REG_BASE          (0x00500000)
#define DMAC1_REG_BASE          (0x00510000)
#define INTC_REG_BASE           (0x00520000)
#define AES_REG_BASE            (0x00530000)
#define GICD_REG_BASE           (0x02001000)
#define GICC_REG_BASE           (0x02002000)
#define CORESIGHT_REG_BASE      (0x03000000)

#define POWER_REG_BASE          (0x04030000)

#define I2S_REG_BASE	        (0x04100000)
#define SPI0_REG_BASE	        (0x04110000)
#define SPI1_REG_BASE	        (0x04120000)
#define SPI2_REG_BASE	        (0x04130000)
#define HASH_REG_BASE	        (0x04140000)
#define TZPC_REG_BASE	        (0x04150000)
#define SPI3_REG_BASE	        (0x04160000)
#define UART0_REG_BASE	        (0x04500000)
#define UART1_REG_BASE	        (0x04510000)
#define UART2_REG_BASE	        (0x04520000)
#define UART3_REG_BASE	        (0x04530000)
#define I2C0_REG_BASE	        (0x04540000)
#define I2C1_REG_BASE	        (0x04550000)
#define I2C2_REG_BASE	        (0x04560000)
#define I2C3_REG_BASE	        (0x04570000)
#define I2C4_REG_BASE	        (0x04580000)
#define PWM_REG_BASE	        (0x04600000)
#define STM0_REG_BASE	        (0x04610000)
#define STM1_REG_BASE	        (0x04620000)
#define WDT_REG_BASE	        (0x04630000)
#define GPIO0_REG_BASE	        (0x04640000)
#define GPIO1_REG_BASE	        (0x04650000)
#define TMR0_REG_BASE	        (0x04660000)
#define TMR1_REG_BASE	        (0x04670000)
#define GPIO2_REG_BASE	        (0x04680000)
#define GPIO3_REG_BASE	        (0x04690000)
#define ACW_REG_BASE	        (0x04700000)
#define EFUSE_REG_BASE	        (0x04710000)
#define SADC_REG_BASE	        (0x04720000)
#define RTC_REG_BASE	        (0x04750000)
#define EPHY_REG_BASE	        (0x0b020000)
#define PERF_REG_BASE	        (0x04830000)
#define TZC400_REG_BASE	        (0x04840000)

#define DDR_SYS_REG_BASE	    (0x04850000)
#define DDR_SYS_RSTN_BASE	    (0x04860000)


#define USBC_REG_BASE	        (0x0BE00000)
#define GMAC_REG_BASE	        (0x0BF00000)
#define SDC0_REG_BASE	        (0x04900000)
#define SDC1_REG_BASE	        (0x04A00000)

#define CPU_CTRL_REG_BASE       (0x01000000)
#define CPU_RESET_REG_BASE      (0x01010000)
#define TOP_CTRL_REG_BASE       (0x04000000)
#define CLK_REG_BASE            (0x04010000)
#define PIN_REG_BASE            (0x04020000)

#define NN_CRTL_REG_BASE        (0x0B000000)
#define NN_RSTN_REG_BASE        (0x0B010000)

#define VEU_SYS_CRTL_REG_BASE        (0x07000000)
#define VEU_SYS_RSTN_REG_BASE        (0x07010000)

#define ISP_SYS_CRTL_REG_BASE        (0x09000000)
#define ISP_SYS_RSTN_REG_BASE        (0x09010000)

/* sys reg io maps */
#define VA_SYS_REG_BASE         (0xFD000000)

#define SYS_REG_V2P(va)         ((va)<<4)
#define SYS_REG_P2V(pa)         ((pa)>>4)

#define VA_CPU_CTRL_REG_BASE    (VA_SYS_REG_BASE + \
					SYS_REG_P2V(CPU_CTRL_REG_BASE))
#define VA_CPU_RESET_REG_BASE         (VA_SYS_REG_BASE + \
					SYS_REG_P2V(CPU_RESET_REG_BASE))

#define VA_TOP_CTRL_REG_BASE    (VA_SYS_REG_BASE + \
					SYS_REG_P2V(TOP_CTRL_REG_BASE))

#define VA_NN_CRTL_REG_BASE     (VA_SYS_REG_BASE + \
					SYS_REG_P2V(NN_CRTL_REG_BASE))
#define VA_NN_RSTN_REG_BASE         (VA_SYS_REG_BASE + \
					SYS_REG_P2V(NN_RSTN_REG_BASE))


#define VA_CLK_REG_BASE         (VA_SYS_REG_BASE + \
					SYS_REG_P2V(CLK_REG_BASE))
#define VA_PIN_REG_BASE         (VA_SYS_REG_BASE + \
					SYS_REG_P2V(PIN_REG_BASE))

#define VA_CPU_CTRL_REG_BASE    (VA_SYS_REG_BASE + \
					SYS_REG_P2V(CPU_CTRL_REG_BASE))
#define VA_CPU_RESET_REG_BASE         (VA_SYS_REG_BASE + \
					SYS_REG_P2V(CPU_RESET_REG_BASE))

#define VA_VEU_SYS_CRTL_REG_BASE    (VA_SYS_REG_BASE + \
					SYS_REG_P2V(VEU_SYS_CRTL_REG_BASE))
#define VA_VEU_SYS_RSTN_REG_BASE         (VA_SYS_REG_BASE + \
					SYS_REG_P2V(VEU_SYS_RSTN_REG_BASE))

#define VA_ISP_SYS_CRTL_REG_BASE    (VA_SYS_REG_BASE + \
					SYS_REG_P2V(ISP_SYS_CRTL_REG_BASE))
#define VA_ISP_SYS_RSTN_REG_BASE         (VA_SYS_REG_BASE + \
					SYS_REG_P2V(ISP_SYS_RSTN_REG_BASE))

#define VA_DDR_SYS_REG_BASE    (VA_SYS_REG_BASE + \
					SYS_REG_P2V(DDR_SYS_REG_BASE))
#define VA_DDR_SYS_RSTN_BASE         (VA_SYS_REG_BASE + \
					SYS_REG_P2V(DDR_SYS_RSTN_BASE))

#define _VA_EPHY_REG_BASE	(VA_SYS_REG_BASE + \
					SYS_REG_P2V(EPHY_REG_BASE))
//CPU_CTRL_REG_BASE
#define REG_PMU_ARC_INTC_MASK   (SYS_REG_P2V(CPU_CTRL_REG_BASE) + 0x0010)
#define REG_PMU_A625_START_CTRL (SYS_REG_P2V(CPU_CTRL_REG_BASE) + 0x0014)
#define REG_PMU_CPU_SYS_MISC    (SYS_REG_P2V(CPU_CTRL_REG_BASE) + 0x0018)
#define REG_PMU_DMA_HDSHAKE_EN  (SYS_REG_P2V(CPU_CTRL_REG_BASE) + 0x0020)

#define REG_PMU_WREN            (SYS_REG_P2V(CPU_CTRL_REG_BASE) + 0x0040)
#define REG_PMU_BOOT_MODE       (SYS_REG_P2V(CPU_CTRL_REG_BASE) + 0x0044)
#define REG_PMU_DDR_SIZE        (SYS_REG_P2V(CPU_CTRL_REG_BASE) + 0x0048)
#define REG_PMU_RESERVED2       (SYS_REG_P2V(CPU_CTRL_REG_BASE) + 0x004C)
#define REG_PMU_CHIP_INFO       (SYS_REG_P2V(CPU_CTRL_REG_BASE) + 0x0050)
#define REG_PMU_EPHY_PARAM      (SYS_REG_P2V(CPU_CTRL_REG_BASE) + 0x0054)
#define REG_PMU_RTC_PARAM       (SYS_REG_P2V(CPU_CTRL_REG_BASE) + 0x0058)
#define REG_PMU_GMAC_TUNING_0   (SYS_REG_P2V(CPU_CTRL_REG_BASE) + 0x007c)
#define REG_PMU_GMAC_TUNING_1   (SYS_REG_P2V(CPU_CTRL_REG_BASE) + 0x0080)
#define REG_PMU_A625BOOT0       (SYS_REG_P2V(CPU_CTRL_REG_BASE) + 0x00A4)
#define REG_PMU_A625BOOT1       (SYS_REG_P2V(CPU_CTRL_REG_BASE) + 0x00A8)
#define REG_PMU_A625BOOT2       (SYS_REG_P2V(CPU_CTRL_REG_BASE) + 0x00AC)
#define REG_PMU_A625BOOT3       (SYS_REG_P2V(CPU_CTRL_REG_BASE) + 0x00B0)

/*ATTENTION: written by ARC */
/* based on history reason, the following register define is not same
 * with document, they are swapped. by PeterJiang.
 */
#define PMU_A625_INT_MASK        (SYS_REG_P2V(CPU_CTRL_REG_BASE) + 0x00B4)
#define PMU_A625_INT_RAWSTAT     (SYS_REG_P2V(CPU_CTRL_REG_BASE) + 0x00B8)
#define PMU_A625_INT_STAT        (SYS_REG_P2V(CPU_CTRL_REG_BASE) + 0x00BC)
#define PMU_ARM_INT_MASK         (SYS_REG_P2V(CPU_CTRL_REG_BASE) + 0x00C0)
#define PMU_ARM_INT_RAWSTAT      (SYS_REG_P2V(CPU_CTRL_REG_BASE) + 0x00C4)
#define PMU_ARM_INT_STAT         (SYS_REG_P2V(CPU_CTRL_REG_BASE) + 0x00C8)


//NN_CRTL_REG_BASE
#define REG_PMU_USB_CFG         (SYS_REG_P2V(NN_CRTL_REG_BASE) + 0x0024)
#define REG_PMU_USB_SYS0        (SYS_REG_P2V(NN_CRTL_REG_BASE) + 0x0028)
#define REG_PMU_USB_SYS1        (SYS_REG_P2V(NN_CRTL_REG_BASE) + 0x002C)
#define REG_PMU_USB_TUNE        (SYS_REG_P2V(NN_CRTL_REG_BASE) + 0x0030)
#define REG_PMU_GMAC_REG        (SYS_REG_P2V(NN_CRTL_REG_BASE) + 0x0038)
#define REG_PMU_EPHY_SEL		(SYS_REG_P2V(NN_CRTL_REG_BASE) + 0x0044)
//NN_RSTN_REG_BASE
#define REG_PMU_NN_CLK_GATE     (SYS_REG_P2V(NN_RSTN_REG_BASE) + 0x0000)
#define REG_PMU_NN_SWRST_CTRL   (SYS_REG_P2V(NN_RSTN_REG_BASE) + 0x0004)
#define REG_PMU_NN_SWRSTN_NSR   (SYS_REG_P2V(NN_RSTN_REG_BASE) + 0x0008)

//TOP_CTRL_REG_BASE
#define REG_PMU_CHIP_ID         (SYS_REG_P2V(TOP_CTRL_REG_BASE) + 0x0000)
#define REG_PMU_IP_VER          (SYS_REG_P2V(TOP_CTRL_REG_BASE) + 0x0004)
#define REG_PMU_FW_VER          (SYS_REG_P2V(TOP_CTRL_REG_BASE) + 0x0008)
#define REG_PMU_WDT_CTRL        (SYS_REG_P2V(TOP_CTRL_REG_BASE) + 0x0010)

#define REG_PMU_PTSLO           (SYS_REG_P2V(TOP_CTRL_REG_BASE) + 0x001C)
#define REG_PMU_PTSHI           (SYS_REG_P2V(TOP_CTRL_REG_BASE) + 0x0020)
#define REG_PMU_USER0           (SYS_REG_P2V(TOP_CTRL_REG_BASE) + 0x0024)

#define REG_PMU_ETHPHY_REG0     (SYS_REG_P2V(TOP_CTRL_REG_BASE) + 0x002c)
#define REG_PMU_ETHPHY_REG1     (SYS_REG_P2V(TOP_CTRL_REG_BASE) + 0x0030)

#define REG_PMU_SCU_PLL_WREN     (SYS_REG_P2V(TOP_CTRL_REG_BASE) + 0x0058)
#define REG_PMU_SDC_MISC         (SYS_REG_P2V(TOP_CTRL_REG_BASE) + 0x006C)

#define REG_DDR_PLL0_CTRL0      (SYS_REG_P2V(DDR_SYS_RSTN_BASE) + 0x0000)
#define REG_DDR_PLL0_CTRL1      (SYS_REG_P2V(DDR_SYS_RSTN_BASE) + 0x0004)
#define REG_DDR_CLK_CTRL        (SYS_REG_P2V(DDR_SYS_RSTN_BASE) + 0x0008)

#define REG_PMU_DDR_SCU_WREN     (SYS_REG_P2V(DDR_SYS_REG_BASE) + 0x0014)


//CLK_REG_BASE
#define REG_PMU_PLL1_CTRL0      (SYS_REG_P2V(CLK_REG_BASE) + 0x0000)
#define REG_PMU_PLL1_CTRL1      (SYS_REG_P2V(CLK_REG_BASE) + 0x0004)
#define REG_PMU_PLL2_CTRL0      (SYS_REG_P2V(CLK_REG_BASE) + 0x0008)
#define REG_PMU_PLL2_CTRL1      (SYS_REG_P2V(CLK_REG_BASE) + 0x000C)
#define REG_PMU_PLL3_CTRL0      (SYS_REG_P2V(CLK_REG_BASE) + 0x0010)
#define REG_PMU_PLL3_CTRL1      (SYS_REG_P2V(CLK_REG_BASE) + 0x0014)
#define REG_PMU_PLL4_CTRL0      (SYS_REG_P2V(CLK_REG_BASE) + 0x0018)
#define REG_PMU_PLL4_CTRL1      (SYS_REG_P2V(CLK_REG_BASE) + 0x001C)
#define REG_PMU_CLK_SEL0        (SYS_REG_P2V(CLK_REG_BASE) + 0x0020)
#define REG_PMU_CLK_SEL1        (SYS_REG_P2V(CLK_REG_BASE) + 0x0024)
#define REG_PMU_CLK_SEL2        (SYS_REG_P2V(CLK_REG_BASE) + 0x0028)
#define REG_PMU_CLK_GATE0       (SYS_REG_P2V(CLK_REG_BASE) + 0x002C)
#define REG_PMU_CLK_GATE1       (SYS_REG_P2V(CLK_REG_BASE) + 0x0030)
#define REG_PMU_CLK_GATE2       (SYS_REG_P2V(CLK_REG_BASE) + 0x0034)
#define REG_PMU_PRE_CLK_GATE    (SYS_REG_P2V(CLK_REG_BASE) + 0x0038)
#define REG_PMU_CLK_DIV0        (SYS_REG_P2V(CLK_REG_BASE) + 0x003C)
#define REG_PMU_CLK_DIV1        (SYS_REG_P2V(CLK_REG_BASE) + 0x0040)
#define REG_PMU_CLK_DIV2        (SYS_REG_P2V(CLK_REG_BASE) + 0x0044)
#define REG_PMU_CLK_DIV3        (SYS_REG_P2V(CLK_REG_BASE) + 0x0048)
#define REG_PMU_CLK_DIV4        (SYS_REG_P2V(CLK_REG_BASE) + 0x004C)
#define REG_PMU_CLK_DIV5        (SYS_REG_P2V(CLK_REG_BASE) + 0x0050)
#define REG_PMU_CLK_DIV6        (SYS_REG_P2V(CLK_REG_BASE) + 0x0054)
#define REG_PMU_SWRST_MAIN_CTRL0 (SYS_REG_P2V(CLK_REG_BASE) + 0x0058)
#define REG_PMU_SWRST_MAIN_CTRL1 (SYS_REG_P2V(CLK_REG_BASE) + 0x005C)
#define REG_PMU_SWRST_AHB_CTRL  (SYS_REG_P2V(CLK_REG_BASE) + 0x0060)
#define REG_PMU_SWRST_APB_CTRL  (SYS_REG_P2V(CLK_REG_BASE) + 0x0064)
#define REG_PMU_SWRSTN_NSR      (SYS_REG_P2V(CLK_REG_BASE) + 0x0068)
#define REG_PMU_SWRSTN_NSR1     (SYS_REG_P2V(CLK_REG_BASE) + 0x006C)
#define REG_PMU_DLL	(SYS_REG_P2V(CLK_REG_BASE) + 0x0078)
#define REG_PMU_CLK_SEL3        (SYS_REG_P2V(CLK_REG_BASE) + 0x007C)

#define REG_PMU_CPU_GATE        (SYS_REG_P2V(CPU_RESET_REG_BASE) + 0x0000)
#define REG_PMU_CPU_SWRST       (SYS_REG_P2V(CPU_RESET_REG_BASE) + 0x0004)
#define REG_PMU_CPU_SWRSTN_NSR  (SYS_REG_P2V(CPU_RESET_REG_BASE) + 0x0008)

#define REG_PMU_ISP_GATE        (SYS_REG_P2V(ISP_SYS_RSTN_REG_BASE) + 0x0000)
#define REG_PMU_ISP_SWRST       (SYS_REG_P2V(ISP_SYS_RSTN_REG_BASE) + 0x0004)

#define REG_PMU_VEU_GATE        (SYS_REG_P2V(VEU_SYS_RSTN_REG_BASE) + 0x0000)
#define REG_PMU_VEU_SWRST       (SYS_REG_P2V(VEU_SYS_RSTN_REG_BASE) + 0x0004)

#define REG_PMU_NN_GATE        (SYS_REG_P2V(NN_RSTN_REG_BASE) + 0x0000)
#define REG_PMU_NN_SWRST       (SYS_REG_P2V(NN_RSTN_REG_BASE) + 0x0004)

#define CONSOLE_REG_BASE		(UART0_REG_BASE)
#define FH_UART_NUMBER			(4)



#define DDRC_IRQ            (1+32)
#define WDT_IRQ             (2+32)
#define TMR0_IRQ            (3+32)
#define VEU_IRQ             (4+32)
#define I2C3_IRQ            (5+32)
#define INTC_IRQ            (6+32)
#define ISP_IRQ             (7+32)
#define LUT2D_IRQ           (8+32)
#define VPU_IRQ             (9+32)
#define NN_IRQ              (10+32)
#define I2C0_IRQ            (11+32)
#define I2C1_IRQ            (12+32)
#define JPEG_IRQ            (13+32)
#define BGM_IRQ			    (14+32)
#define VEU_LOOP_IRQ        (15+32)
#define AES_IRQ			    (16+32)
#define VICAP_IRQ		    (17+32)
#define TMR1_IRQ            (18+32)
#define ACW_IRQ			    (19+32)
#define I2C4_IRQ		    (20+32)
#define SPI1_IRQ		    (21+32)
#define JPEG_LOOP_IRQ	    (22+32)
#define VGS_IRQ		    (23+32)
#define DMAC1_IRQ		    (24+32)
#define I2S0_IRQ		    (25+32)
#define SPI3_IRQ		    (26+32)
#define AVE_IRQ		    (27+32)
#define SPI0_IRQ		    (28+32)
#define ARC_SW_IRQ		    (29+32)
#define VOU_IRQ		    (30+32)
#define UART1_IRQ		    (31+32)
#define ARM_SW_IRQ		    (32+32)
#define RTC_IRQ			    (33+32)
#define STM_H_IRQ		    (34+32)
#define STM_V_IRQ	        (35+32)
#define PWM_IRQ			    (36+32)
#define TZC400_IRQ           (37+32)
#define SPI2_IRQ		    (38+32)
#define USBC_IRQ		    (39+32)
#define GPIO1_IRQ		    (40+32)
#define UART2_IRQ		    (41+32)
#define SDC0_IRQ		    (42+32)
#define SDC1_IRQ		    (43+32)
#define GMAC_IRQ		    (44+32)
#define EPHY_IRQ		    (45+32)
#define I2C2_IRQ		    (46+32)
#define RTC_ALM_IRQ         (47+32)
#define RTC_CORE_IRQ        (48+32)
#define HASH_IRQ            (49+32)
#define UART0_IRQ            (50+32)
#define PERF_IRQ             (51+32)
#define SADC_IRQ             (52+32)
#define GPIO0_IRQ             (53+32)
#define GPIO2_IRQ             (54+32)
#define UART3_IRQ           (55+32)
#define PMU_IRQ             (56+32)
#define PMU1_IRQ             (57+32)
#define DMAC0_IRQ		    (58+32)

#define MEM_START_PHY_ADDR	DDR_BASE
#define MEM_SIZE			0x4000000


#define NR_INTERNAL_IRQS	(64)
#define NR_EXTERNAL_IRQS	(64)

/* CPU RESET */
#define A7_RSTN_BIT             (0)
#define ARC_RSTN_BIT			(1)
#define DMAC0_RSTN_BIT			(2)
#define DMAC1_RSTN_BIT			(3)
#define INTC_RSTN_BIT			(4)
#define AES_RSTN_BIT			(5)
#define EMC_RSTN_BIT			(6)


#define HASH_DMA_HANDSHAKE  (14)
/* timer clk  fpga 1M,soc 50M*/
#ifdef CONFIG_FPGA
#define TIMER_CLK			(1000000)
#else
#define TIMER_CLK			(50000000)
#endif

/*sdio*/
#define SIMPLE_0     (0)
#define SIMPLE_22    (1)
#define SIMPLE_45    (2)
#define SIMPLE_67    (3)
#define SIMPLE_90    (4)
#define SIMPLE_112   (5)
#define SIMPLE_135   (6)
#define SIMPLE_157   (7)
#define SIMPLE_180   (8)
#define SIMPLE_202   (9)
#define SIMPLE_225   (10)
#define SIMPLE_247   (11)
#define SIMPLE_270   (12)
#define SIMPLE_292   (13)
#define SIMPLE_315   (14)
#define SIMPLE_337   (15)

/*usb*/
#define USB_UTMI_RST_BIT      (0x1<<4)
#define USB_PHY_RST_BIT       (0x11)
#define USB_SLEEP_MODE_BIT    (0x1<<24)
#define USB_IDDQ_PWR_BIT    (0x1<<10)
#define USB_TUNE_ADJ_SET    (0x78203344)


#define CLK_SCAN_BIT_POS                (28)
#define INSIDE_PHY_ENABLE_BIT_POS       (0)
#define MAC_REF_CLK_DIV_MASK            (0x0f)
#define MAC_REF_CLK_DIV_BIT_POS         (24)
#define MAC_PAD_RMII_CLK_MASK           (0x0f)
#define MAC_PAD_RMII_CLK_BIT_POS        (24)
#define MAC_PAD_MAC_REF_CLK_BIT_POS     (28)
#define ETH_REF_CLK_OUT_GATE_BIT_POS    (25)
#define ETH_RMII_CLK_OUT_GATE_BIT_POS   (28)
#define IN_OR_OUT_PHY_SEL_BIT_POS       (26)
#define INSIDE_CLK_GATE_BIT_POS         (0)
#define INSIDE_PHY_SHUTDOWN_BIT_POS     (31)
#define INSIDE_PHY_RST_BIT_POS          (30)
#define INSIDE_PHY_TRAINING_BIT_POS     (27)
#define INSIDE_PHY_TRAINING_MASK        (0x0f)

#define TRAINING_EFUSE_ACTIVE_BIT_POS          4
#define EPHY_PASS_CHECK_BIT_POS          0

#define PMU_DWI2S_CLK_SEL_REG   (REG_PMU_CLK_SEL2)
#define PMU_DWI2S_CLK_SEL_SHIFT (18)
#define PMU_DWI2S_CLK_DIV_REG   (REG_PMU_CLK_DIV5)
#define PMU_DWI2S_CLK_DIV_SHIFT (14)

/* SWRST_AHB_CTRL */
#define TOP_HRSTN_BIT			(0)
#define SDC0_HRSTN_BIT			(1)
#define SDC1_HRSTN_BIT			(2)

#define SD1_FUNC_SEL_MAP	{3, 0, 2, 1}

#endif /* __FULLHAN_CHIP_H__ */
